Semiconductor power optimization, power integrity and reliability

Semiconductor power

Semiconductors are the backbone of every single electronic device we may be taking for granted. Our computers, our smartphones, all electronic devices are powered by a bed of silicon which in turn is covered with millions and billions of transistors. These transistors are thinner than your strand of hair and are composed of something called a semiconductor. 

Last year, there was a lot of growth in semiconductor innovation and in the AI/ML sector. A lot of newer opportunities are being created even now thanks to the growth of 5G and AR/VR in gaming and industrial sectors. This means that there is a need for higher reliability with autonomous technologies. Sectors like mobile, data centres, and high-performance computing also require it.

Talking about the semiconductors, the IRDS establishes a 5 nm (nanometer) node as the MOSFET (metal–oxide–semiconductor field-effect transistor) technology node following the 7 nm node and a 7 nm node following the 10 nm.  

The transition to 5/3nm and beyond, as well as the low-voltage dynamics and yield robustness associated with them, has been a big jump and learning experience for customers. With respect to power rail analysis, more attention has been given to design robustness and reliability for an increasing number of companies, especially at lower nodes. Power integrity issues are increasingly included as a primary concern rather than an afterthought. This is a bigger concern as more companies are now exploring 3DIC designs.

Any design that involves the usage of advanced nodes FinFETs (fin field-effect transistors) like the 7 nm nodes becomes more complex than it was with the prior nodes. Unlike the prior nodes, the secondary physical impacts are significant enough to be written-off as negligible. The margin-based methodologies worked good in the past but cannot be considered any more effective. These methodologies assisted in circumscribing the problem space by dissociating the design methodologies so as to manage limitations and complexity in EDA (Electronic Design Automation) tools not designed to find a solution to multiphysics challenges. It impacts not only the TTR (time-to- result) but also the TTM (time-to-market) goals in the complex design projects.

The design challenges resulting from EM/IR can no longer be addressed at the very end of the design cycle. EM/IR needs to be thoughtfully built into the design process right from the beginning. ‘Shifting Left’ is required to drive the right methods into the process. ANSYS’ simulation block designer has the power to not only analyze but also fix issues early in the design cycle at the block level before full-chip integration. This has provided significant productivity benefits.

The Solution

Enabling ANSYS RedHawk Analysis Fusion earlier in physical design flows will help designers to achieve 5X increase in productivity and faster convergence during signoff with better QoR. This is by using ANSYS’ industry-standard power integrity and reliability analyses. 

Thus, leveraging sign-off-quality solutions during the in-design phase provides early visibility into design issues and allows them to be fixed then and there. Specially, new innovative placement, clock tree synthesis, and post-route IR-driven optimization strategies have enabled users to reduce manual work and maximize design robustness through IR recovery. Designers are able to eliminate 95% of IR drop violations using ANSYS RedHawk Analysis Fusion on a large graphics processor design.

The in-design rail flow enabled by ANSYS RedHawk Analysis Fusion allows the P&R engineering team to easily run the RedHawk engines under the hood and automatically deliver signoff-quality results back to IC Compiler II for fixing. This drives better decisions for achieving PPA goals early. Also, thermal reliability is a key concern in FinFET designs. By enabling self-heating analysis during in-design, physical design engineers can analyze and fix reliability issues earlier by doing thermal-aware EM checks.

In conclusion, 7nm node designs are without a doubt subject to a much more complex multiphysics environment. For a strong silicon tape-out, it will be important to address their impact on the delay variability. Thanks to engineering simulation, these can be addressed upfront.